This invention relates to data processors operated on a time shared basis, and particularly to such processors employed for the control of telecommunication switching systems.
Such data processors are known to comprise sets of registers for storing partial results, the current instruction, the address of the next instruction, and all other information normally known as the program context, an arithmetic and logic unit which performs data handling and logical operations, and a store or plurality of stores in which data and program instructions are held. A processor has both way connections to peripheral devices providing input data.
When a data processor is operated by a time division multiplex (TDM) input, comprising therefore a sequence of channels operating in a cyclic manner, each channel has the facility of being operated upon by a different program if desired. It is known that in order to synchronise a processor to a high speed TDM system it is necessary to have program interrupts. A processor requires a certain minimum time in order to preserve details of one program applicable to one channel before starting another program for a different channel, and this limits the maximum rate at which program changes can be accepted.
Known processors operating with such a TDM system comprise a group of registers, each register being in respect of a different program function and having a capacity for storing the data of a single channel only, but such that the group of registers is associated cyclically in synchronism with the sequence of channel inputs. Thus each register is capable of receiving and storing information only during an individual channel time. When a register has been associated with a first channel, and then a second channel starts, a program interrupt is required in order to transfer from the register the value appropriate to the first channel and insert it in a store individual to the first channel, leaving the register empty and free to be associated with the second channel. When, in the channel input cycle, the register is again associated with the first channel, the value in the store of the first channel is transferred back into the register.
The time taken to transfer the value from the register to the store and back from the store to the register, is a disadvantage in that it limits the time available for program execution during a given channel time.
The object of the present invention is to overcome this disadvantage by making program interrupts unnecessary.